The present invention relates to a bit clock signal generator for use in a digital signal demodulator, which comprises means for generating a detection window pulse having a predetermined pulse width shorter than a period of a bit clock signal from either of time points of rise and fall of the waveform of a signal to be demodulated, or from both the time points thereof, the signal to be demodulated being a digital signal modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including a phase information of a bit clock signal to deliver the detection window pulse to a phase locked loop including a pphase comparison circuit and a voltage controlled oscillator as a comparison wave, thus allowing the voltage controlled oscillator to generate a bit clock signal.
Namely, the present invention relates to a digital audio tape recording system known as the R-DAT, abbreviated after a rotary head digital audio tape system. On the tape which has been recorded using such R-DAT, signals conforming to the R-DAT industry standards are recorded. Such recording signals are recorded at a standard tape speed prescribed by the industry standards.
It is well known that in recording and transmitting a digital signal, the digital signal subject to the recording and transmission is to be recorded and transmitted with the digital signal being modulated by a particular modulation system selected from various modulation systems. In demodulating a signal subject to demodulation, i.e., a signal to be demodulated which has been modulated in accordance with a particular modulation system as mentioned above, a bit clock signal is required. In dependence upon the kind of a modulation system employed, there are instances where phase information of a bit clock is only intermittently included in a signal subject to demodulation.
In general, such a bit clock signal necessary at the time of demodulation is derived from a signal to be demodulated. However, for a digital signal constituted with a periodical signal which includes intermittently phase information of the bit clock signal, merely employment of a phase locked loop of the ordinary construction fails to derive a bit clock signal. This is readily understood in light of the fact that phase information of a bit clock signal only intermittently exists in a signal to be modulated.
For a bit clock signal generator capable of generating a bit clock signal necessary at the time of demodulation derived from a signal to be demodulated of a digital signal constituted with a periodical signal which contains intermittently phase information of a bit clock signal, signal generators of various configurations have been conventionally proposed. The applicant company have also proposed bit clock signal generator for use in digital signal demodulator as disclosed in, e.g., U.S. Pat. No. 4,628,282 issued to the present applicant and U.S. Pat. No. 4,617,526 (Victor) etc. for a bit clock signal generator for use in a digital signal demodulator comprising means for generating a detection window pulse having a predetermined pulse width shorter than a period of a bit clock signal from either of time points of rise and fall of the waveform of a signal to be demodulated, or from the both time points thereof, the signal to be demodulated being a digital signal modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including a phase information of the bit clock signal to deliver the detection window pulse to a phase locked loop including a phase comparison circuit and a voltage controlled oscillator, as a comparison wave, thus allowing the voltage controlled oscillator in the phase locked loop to generate a bit clock signal. Moreover, in the case of a signal such that a signal subject to demodulation is intermittent on the time axis with having a relatively long period during which no signal exists, i.e., "relatively long no signal period", e.g., in the case of a signal having a long no signal period, such as a signal obtained by recording and reproducing a digital signal having been modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including phase information of a bit clock signal on a magnetic tape wound around the rotary cylinder at a winding angle of 90 degrees by using two magnetic heads provided at positions which have symmetry of 180 degrees (positions where an angular distance is 180 degrees) around the rotary cylinder in a rotary head type magnetic recording and reproducing equipment, the problem with the previously proposed bit clock signal generator for use in a digital signal demodulator is that when the phase locked loop is unlocked during a long no signal period, it takes long time until the phase locked loop recovers into a locked condition by a signal which appears again after the no signal period has elapsed, whereby a demodulated signal is disturbed. The applicant of this invention has proposed a digital signal demodulator provided with a bit clock signal generator which has solved such a problem in U.S. Pat. No. 4,672,329 (Victor). In a digital signal demodulator provided with a bit clock signal generator and a digital signal demodulator provided with the abovementioned bit clock signal generator, the first-mentioned bit clock signal generator comprising: means for generating a detection window pulse having a predetermined pulse width shorter than a period of a bit clock signal from either of time points of rise and fall of the waveform of a signal subject to demodulation, or from both the time points thereof, the signal subject to demodulation being a digital signal having been modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including a phase information of the bit clock signal; means for delivering, as a comparison wave, the detection window pulse to a phase locked loop including a phase comparison circuit and a voltage controlled oscillator; a first pulse source for generating a first pulse having a period T1; a second pulse source for generating a second pulse having a period T2 which has the relationship of T2&lt;T1 with respect to the period T1 of the first pulse generated in the first pulse source; first measurement means for measuring the period T1 of the first pulse generated in the first pulse source with a bit clock signal obtained from the voltage controlled oscillator in the phase locked loop being as a reference pulse for measurement, second measurement means for measuring the period T2 of the second pulse generated in the second pulse source with a bit clock signal obtained from the voltage controlled oscillator in the phase locked loop being as a reference pulse for measurement; means for producing a first signal when a measured value N1 defined as a value obtained by counting the period T1 of the first pulse having been generated in the first pulse source using the reference pulse is less than a minimum value N1s determined in correspondence with a first allowed variable range of an oscillating frequency in the voltage controlled oscillator, and for producing a second signal when the measured value N1 is larger than a maximum value N1l determined in correspondence with the first allowed variable range of the oscillating frequency; means for producing a third signal when a measured value N2 defined as a value obtained by counting the period T2 of the second pulse having been generated in the second pulse source using the reference pulse is less than a minimum value N2s determined in correspondence with a second allowed variable range of an oscillating frequency set so as to have a frequency change rate larger than a frequency change rate in the first allowed variable range set for the oscillating frequency of the voltage controlled oscillator, and for producing a fourth signal when the measured value N2 is larger than a maximum value N2l determined in correspondence with the second allowed variable range of the oscillating frequency in the voltage controlled oscillator; means for obtaining a first error signal using the first and third signals; means for obtaining a second error signal using the second and fourth signals; and means for controlling an error signal of the phase comparison circuit in the phase locked loop using the respective error signals, this signal demodulator provided with the bit clock signal generator is characterized in that it comprises means for selectively allowing either of the first and second signals or both the signals to be invalid. In addition, the applicant of this invention has also proposed in Japanese patent application No. 30119/1986 a digital signal recording and reproducing equipment capable of controlling a running speed of the magnetic tape for permitting retrieval of an ETM (eight-to-ten modulation) signal from the magnetic tape with the magnetic tape being caused to run at a speed larger than a speed at the time of recording in the above-mentioned rotary magnetic head type magnetic recording/reproducing equipment.
As previously mentioned, a bit rate of a signal subject to demodulation obtained by running a magnetic tape from which a digital signal having been modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including phase information of a bit clock signal is reproduced at a tape speed different from that at the time of recording, by using two rotary magnetic heads rotating at the same rotational speed as that at the time of recording will be different from a bit rate of a signal subject to demodulation at the time of an ordinary reproducing mode to reproduce a digital signal by using two rotary magnetic heads rotating at the same rotational as that at the time of recording from the magnetic tape caused to run at the same running speed as that at the time of recording.
Also as previously described, a bit clock signal is required for demodulating a signal subject to demodulation. However, with the conventional bit clock signal generator to generate a detection window pulse having a predetermined pulse width shorter than a period of a bit clock signal from either of time points of rise and fall of the waveform of a signal subject to demodulation, or from both the time points thereof for generating a bit clock signal necessary at the time of demodulation from the signal subject to demodulation of a digital signal constituted with a periodical signal only intermittently including a phase information of the bit clock signal to deliver the detection window pulse to a phase locked loop including a phase comparison circuit and a voltage controlled oscillator as a signal wave to be compared with, thus generating a bit clock signal from the voltage controlled oscillator in the phase locked loop, there occurs a problem that since the pulse width of the detection window pulse to be phase-compared with the bit clock signal outputted from the voltage controlled oscillator in the phase comparison circuit of the phase locked loop, is fixed even when the bit rate of the signal subject to demodulation varies, difficulty in making a normal phase comparison, prolonged lock-in time, lowered detection margin and the like would occur when the bit rate of the signal subject to demodulation changes.
The above-mentioned problem will be explained with reference to the attached drawings. FIG. 6 shows a phase comparison circuit PC as shown in FIG. 3 in U.S. Pat. No. 4,628,282. The circuit arrangement shown in FIG. 6 includes an input terminal 3 for a bit clock signal Pc, an input terminal 4 for a detection window pulse Pw, Dtype flip-flops 5 and 6, inverters 7 and 8, and resistors 9 to 12.
A phase error signal outputted from the phase comparison circuit PC shown in FIG. 6 is delivered to a voltage controlled oscillator via a low-pass filter. A signal outputted from the voltage controlled oscillator is used as a bit clock signal Pc and is also delivered to the terminal 3 of the phase comparison circuit PC.
In FIGS. 7 to 9, the waveform of each item (a) denotes a signal subject to demodulation (labeled DATA), that of each item (b) a detection window pulse Pw, and that of each item (c) a bit clock signal Pc. FIG. 7 shows that the signal subject to demodulation has a normal bit rate, FIG. 8 shows that it has a bit rate higher than the normal bit rate, and FIG. 9 shows that it has a bit rate lower than the normal bit rate.
An attention is now drawn to the case where the pulse width of the detection window pulse Pw is fixed even when the bit rate of a signal subject to demodulation changes, as shown in FIGS. 7 to 9. Under this circumstance, when the bit rate of the signal subject to demodulation is higher than the ordinary bit rate as shown in FIG. 8, the pulse width of the detection pulse Pw becomes too broad as compared to the pulse width of the bit clock signal Pc, resulting in failure in the normal phase comparison. In contrast, when the bit rate of the signal subject to demodulation is lower than the ordinary bit rate as shown in FIG. 9, the pulse width of the detection pulse Pw becomes too narrow as compared to the pulse width of the bit clock signal Pc, with the result that the pulse width of the phase error signal becomes narrow, the lock-in time is prolonged, and the detection margin for demodulation is lowered.
In the case of a reproduced signal from a magnetic recording/reproducing equipment adapted to effect a speed control of the magnetic tape while reading data at the time of the fast forward rewind operation, an increase of jitter of a signal subject to demodulation occurs due to the fact that the load to the tape transport system becomes heavy at the time of the rewinding/fast-feeding operation, and changes of the load of the running tape with respect to the head cylinder due to speed unevenness produce jitter in the rotation of the head cylinder, with the result that the jitter of the signal subject to demodulation is increased, thus leading to lowering of the detection margin.